Altium

Design Rule Verification Report

Date	:	3/9/2015
Time	:	3:36:31 PM
Elapsed Time	:	00:00:05
Filename	:	D:\Project Files\TIDA-00490_test\Design Files\20150309\TIDA-00490\TIDA-00490_AC_Binary.PcbDoc

Warnings	:	0
Rule Violations	:	2

Summary

Warnings	Count
Total	0

Rule Violations	Count
Short-Circuit Constraint (Allowed=Yes) (InNet('GND')),(InNet('GND1'))	0
Clearance Constraint (Gap=10mil) (All),(All)	0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=20mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Routing Layers(All)	0
Routing Via (MinHoleWidth=8mil) (MaxHoleWidth=12mil) (PreferredHoleWidth=8mil) (MinWidth=20mil) (MaxWidth=24mil) (PreferedWidth=20mil) (IsVia and InAnyComponent)	0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=31.496mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=62.992mil) (PreferedWidth=32mil) (All)	0
Un-Routed Net Constraint ( (All) )	0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent)	0
Minimum Annular Ring (Minimum=7mil) (All)	0
Hole Size Constraint (Min=8mil) (Max=251mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Clearance Constraint (Gap=12mil) (IsVia),(IsVia)	0
Clearance Constraint (Gap=8mil) (IsSMTPin),(IsVia)	2
Clearance Constraint (Gap=25mil) (InPolygon),(InPolygon)	0
Clearance Constraint (Gap=12mil) (InPolygon),(IsTrack and IsSMTPin and IsVia)	0
Total	2

Clearance Constraint (Gap=8mil) (IsSMTPin),(IsVia)
Via (2090mil,265mil) Top Layer to Bottom Layer	Pad Q1-D(2003.858mil,320mil) Top Layer
Via (2090mil,765mil) Top Layer to Bottom Layer	Pad Q2-D(2003.858mil,815mil) Top Layer